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IS24C01-2 IS24C01-3 IS24C02-2 IS24C02-3 IS24C04-2 IS24C04-3 IS24C08-2 IS24C08-3 IS24C16-2 IS24C16-3
1K-bit/2K-bit/4K-bit/8K-bit/16K-bit 2-WIRE SERIAL CMOS EEPROM
FEATURES
* Low Power CMOS Technology -- Standby Current less than 8 A (5.5V) -- Read Current (typical) less than 1 mA (5.5V) -- Write Current (typical) less than 3 mA (5.5V) * Low Voltage Operation -- IS24C01-2, IS24C02-2, IS24C04-2 IS24C08-2 & IS24C16-2: Vcc = 1.8V to 5.5V -- IS24C01-3, IS24C02-3, IS24C04-3, IS24C08-3 & IS24C16-3: Vcc = 2.5V to 5.5V * 100 KHz (1.8V) and 400 KHz (5V) Compatibility * Hardware Data Protection -- Write Protect Pin * Sequential Read Feature * Filtered Inputs for Noise Suppression * 8-pin PDIP and 8-pin SOIC packages * 8-pin TSSOP (1K,2K & 8K only) * 8-pin MSOP (1K,2K only) * Self time write cycle with auto clear -- 5 ms @ 2.5V
ISSI
SEPTEMBER 2001
(R)
* Organization: -- IS24C01-2 and IS24C01-3: 128x8 (one block of 128 bytes) -- IS24C02-2 and IS24C02-3: 256x8 (one block of 256 bytes) -- IS24C04-2 and IS24C04-3: 512x8 (two blocks of 256 bytes) -- IS24C08-2 and IS24C08-3: 1024x8 (four blocks of 256 bytes) -- IS24C16-2 and IS24C16-3: 2048x8 (eight blocks of 256 bytes) * Page Write Buffer * Two-Wire Serial Interface -- Bi-directional data transfer protocol * High Reliability -- Endurance: 1,000,000 Cycles -- Data Retention: 100 Years * Commercial and Industrial temperature ranges
PRODUCT OFFERING OVERVIEW
Part No IS24C01-2 IS24C01-3 IS24C02-2 IS24C02-3 IS24C04-2 IS24C04-3 IS24C08-2 IS24C08-3 IS24C16-2 IS24C16-3 Voltage 1.8V-5.5V 2.5V-5.5V 1.8V-5.5V 2.5V-5.5V 1.8V-5.5V 2.5V-5.5V 1.8V-5.5V 2.5V-5.5V 1.8V-5.5V 2.5V-5.5V Speed 100 KHz 400 KHz 100 KHz 400 KHz 100 KHz 400 KHz 100 KHz 400 KHz 100 KHz 400 KHz Standby ICC < 4 A < 8 A < 4 A < 8 A < 4 A < 8 A < 4 A < 8 A < 4 A < 8 A Read ICC 1 mA 1 mA 1 mA 1 mA 1 mA 1 mA 1 mA 1 mA 1 mA 1 mA Write ICC 3 mA 3 mA 3 mA 3 mA 3 mA 3 mA 3 mA 3 mA 3 mA 3 mA Temperature C,I C,I C,I C,I C,I C,I C,I C,I C,I C,I
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. C 09/01/2001
1
IS24C01-2 IS24C01-3 IS24C02-2 IS24C02-3 IS24C04-2 IS24C04-3 IS24C08-2 IS24C08-3 IS24C16-2 IS24C16-3
DESCRIPTION
The IS24C01-2 is a 1.8V 1K-bit EEPROM, IS24C01-3 is a 2.5V 1K-bit EEPROM, IS24C02-2 is a 1.8V 2K-bit EEPROM, IS24C02-3 is a 2.5V 2K-bit EEPROM, IS24C042 is a 1.8V 4K-bit EEPROM, IS24C04-3 is a 2.5V 4K-bit EEPROM, IS24C08-2 is a 1.8V 8K-bit EEPROM, IS24C083 is a 2.5V 8K-bit EEPROM, IS24C16-2 is a 1.8V 16K-bit EEPROM, and the IS24C16-3 is a 2.5V 16K-bit EEPROM.
ISSI
(R)
The IS24CXX (IS24C01-2, IS24C01-3, IS24C02-2, IS24C02-3, IS24C08-2, IS24C08-3, IS24C16-2 and IS24C16-3) family is a low-cost and low voltage 2-wire Serial EEPROM. It is fabricated using ISSI's advanced CMOS EEPROM technology and provides a low power and low voltage operation. The IS24CXX family features a write protection feature, and is available in 8-pin DIP and 8-pin SOIC packages. The IS24C01 and IS24C02 are available in 8-pin MSOP package. The IS24C01, IS24C02 and IS24C08 are available in 8-Pin TSSOP package.
FUNCTIONAL BLOCK DIAGRAM
Vcc 8
HIGH VOLTAGE GENERATOR, TIMING & CONTROL
SDA 5 WP 7 SLAVE ADDRESS REGISTER & COMPARATOR WORD ADDRESS COUNTER
X DECODER
SCL 6
CONTROL LOGIC
EEPROM ARRAY
Y DECODER
GND 4 nMOS
ACK
Clock DI/O
>
DATA REGISTER
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. C 09/01/2001
2
IS24C01-2 IS24C01-3 IS24C02-2 IS24C02-3 IS24C04-2 IS24C08-2 IS24C08-3 IS24C16-2
PIN CONFIGURATION
8-Pin DIP and SOIC 8 Pin TSSOP (1K, 2K and 8K) 8-Pin MSOP (1K, 2K)
IS24C04-3 IS24C16-3
ISSI
(R)
A0 A1 A2 GND
1 2 3 4
8 7 6 5
VCC WP SCL SDA
PIN DESCRIPTIONS
A0-A2 SDA SCL WP Vcc GND Address Inputs Serial Address/Data I/O Serial Clock Input Write Protect Input Power Supply Ground The IS24C04-2 and IS24C04-3 uses A1 and A2 pins for hardwire addressing and a total of four devices may be addressed on a single bus system. The A0 pin is not used by IS24C04-2 or IS24C04-3. This pin can be left floating or tied to GND or Vcc. The IS24C08-2 and IS24C08-3 only use A2 input for hardwire addressing and a total of two devices may be addressed on a single bus system. The A0 and A1 pins are not used by IS24C08-2 and IS24C08-3. They may be left floating or tied to either GND or Vcc. These pins are not used by IS24C16-2 and IS24C16-3. A0 and A1 may be left floating or tied to either GND or Vcc. A2 should be tied to either GND or Vcc. WP WP is the Write Protect pin. On the 24C01, 24C0, IS24C04 and 24C08, if the WP pin is tied to VCC the entire array becomes Write Protected (Read only). On the 24C16, if the WP pin is tied to Vcc the upper half array becomes Write Protected (Read only). When WP is tied to GND or left floating normal read/write operations are allowed to the device.
SCL This input clock pin is used to synchronize the data transfer to and from the device. SDA The SDA is a Bi-directional pin used to transfer addresses and data into and out of the device. The SDA pin is an open drain output and can be wire-Ored with other open drain or open collector outputs. The SDA bus requires a pullup resistor to Vcc. A0, A1, A2 The A0, A1 and A2 are the device address inputs. The IS24C01 and IS24C02 use the A0, A1, and A2 for hardware addressing and a total of 8 devices may be used on a single bus system.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. C 09/01/2001
3
IS24C01-2 IS24C01-3 IS24C02-2 IS24C02-2 IS24C04-2 IS24C04-3 IS24C08-2 IS24C08-3 IS24C16-2 IS24C16-3
DEVICE OPERATION
The IS24CXX family features a serial communication and supports a bi-directional 2-wire bus transmission protocol. 2-WIRE BUS The two-wire bus is defined as a Serial Data line(SDA), and a Serial Clock Line (SCL). The protocol defines any device that sends data onto the SDA bus as a transmitter, and the receiving devices as a receiver. The bus is controlled by MASTER device which generates the SCL, controls the bus access and generates the STOP and START conditions. The IS24CXX is the SLAVE device on the bus. The Bus Protocol: -- Data transfer may be initiated only when the bus is not busy -- During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. The state of the data line represents valid data when after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. START Condition The START condition precedes all commands to the devices and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The IS24CXX monitors the SDA and SCL lines and will not respond until the START condition is met. STOP Condition The STOP condition is defined as a LOW to HIGH transition of SDA when SCL is HIGH. All operations must end with a STOP condition. ACKnowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line. DEVICE ADDRESSING The MASTER begins a transmission by sending a START condition. The MASTER then sends the address of the particular slave devices it is requesting. The SLAVE address is 8 bits. The four most significant bits of the address are fixed as 1010 for the IS24CXX. For the IS24C16-2 and IS24C16-3, the bits(B2, B1 and B0) are used for memory page addressing (the IS24C16-2 and 4
ISSI
(R)
IS24C16-3 are organized as eight blocks of 256 bits). For the IS24C04-2 and IS24C04-3 out of the next three bits, B0 is for Memory Page Addressing (the IS24C04-2 and IS24C04-3 are organized as two blocks of 256 bits) and A2 and A1 bits are used as device address bits and must compare to its hard-wire inputs pins (A2 and A1). Up to four IS24C08's may be individually addressed by the system. The page addressing bits for IS24Cxx should be considered the most significant bits of the data word address which follows. For the IS24C08-2 and IS24C08-3 out of the next three bits, B1 and B0 are for memory page addressing (the IS24C08-2 and IS24C08-3 are organized as four blocks of 256 bits) and the A2 bit is used as device address bit and must compare to its hard-wired input pin (A2). Up to two IS24C08 may be individually addressed by the system. The page addressing bits for IS24CXX should be considered the most significant bits of the data word address which follows. For the IS24C01/2-2 and IS24C01/2-3, the A0, A1, and A2 are used as device address bits and must compare to its hard-wired input pins (A0, A1, and A2) Up to Eight IS24C01/2's may be individually addressed by the system. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. After the MASTER sends a START condition and the SLAVE address byte, the IS24CXX monitors the bus and responds with an Acknowledge (on the SDA line) when its address matches the transmitted slave address. The IS24CXX pulls down the SDA line during the ninth clock cycle, signaling that it received the eight bits of data. The IS24CXX then performs a Read or Write operation depending on the state of the R/W bit. WRITE OPERATION Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information(with the R/W set to Zero) to the Slave device. After the Slave generates an acknowledge, the Master sends the byte address that is to be written into the address pointer of the IS24CXX. After receiving another acknowledge from the Slave, the Master device transmits the data byte to be written into the address memory location. The IS24CXX acknowledges once more and the Master generates the STOP condition, at which time the device begins its internal programming cycle. While this internal cycle is in progress, the device will not respond to any request from the Master device.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. C 09/01/2001
IS24C01-2 IS24C01-3 IS24C02-2 IS24C02-3 IS24C04-2 IS24C08-2 IS24C08-3 IS24C16-2
IS24C04-3 IS24C16-3
ISSI
(R)
Page Write The IS24CXX is capable of page-WRITE (8-byte for 24C01/2 and 16-byte for 24C04/08/16) operation. A pageWRITE is initiated in the same manner as a byte write, but instead of terminating the internal write cycle after the first data word is transferred, the master device can transmit up to N more bytes (N=7 for 24C01/2 and N=15 for 24C04/ 08/16). After the receipt of each data word, the IS24CXX responds immediately with an ACKnowledge on SDA line, and the three lower (24C01/24C02) or four lower (24C04/ 24C08/24C16) order data word address bits are internally incremented by one, while the higher order bits of the data word address remain constant. If the master device should transmit more than N+1 (N=7 for 24C01/2 and N=15 for 24C04/08/16) words, prior to issuing the STOP condition, the address counter will "roll over," and the previously written data will be overwritten. Once all N+1 (N=7 for 24C01/2 and N=15 for 24C04/08/16) bytes are received and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the IS24CXX in a single write cycle. All inputs are disabled until completion of the internal WRITE cycle. Acknowledge Polling The disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host's write operation, the IS24CXX initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the IS24CXX is still busy with the write operation, no ACK will be returned. If the IS24CXX has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation.
maintains the address of the last byte accessed, incremented by one. For example, if the previous operation is either a read or write operation addressed to the address location n, the internal address counter would increment to address location n+1. When the IS24CXX receives the Device Addressing Byte with a READ operation (read/write bit set to "1"), it will respond an ACKnowledge and transmit the 8-bit data word stored at address location n+1. The master will not acknowledge the transfer but does generate a STOP condition and the IS24CXX discontinues transmission. If 'n' is the last byte of the memory, then the data from location '0' will be transmitted. (Refer to Current Address Read Diagram.) Random Access Read Selective READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a 'dummy' write operation by sending the START condition, slave address and word address of the location it wishes to read. After the IS24CXX acknowledge the word address, the Master device resends the START condition and the slave address, this time with the R/W bit set to one. The IS24CXX then responds with its acknowledge and sends the data requested. The master device does not send an acknowledge but will generate a STOP condition. (Refer to Random Address Read Diagram.) Sequential Read Sequential Reads can be initiated as either a Current Address Read or Random Address Read. After the IS24CXX sends initial byte sequence, the master device now responds with an ACKnowledge indicating it requires additional data from the IS24CXX. The IS24CXX continues to output data for each ACKnowledge received. The master device terminates the sequential READ operation by pulling SDA HIGH (no ACKnowledge) indicating the last data word to be read, followed by a STOP condition. The data output is sequential, with the data from address n followed by the data from address n+1, ... etc. The address counter increments by one automatically, allowing the entire memory contents to be serially read during sequential read operation. When the memory address boundary (127 for IS24C01-2 and IS24C01-3; 255 for IS24C02-2 and IS24C02-3; 511 for IS24C04-2 and IS24C02-3; 1023 for IS24C08-2 and IS24C08-3; 2047 for IS24C16-2 and IS24C16-3) is reached, the address counter "rolls over" to address 0, and the IS24CXX-2 continues to output data for each ACKnowledge received. (Refer to Sequential Read Operation Starting with a Random Address READ Diagram.)
READ OPERATION
READ operations are initiated in the same manner as WRITE operations, except that the read/write bit of the slave address is set to "1". There are three READ operation options: current address read, random address read and sequential read. Current Address Read The IS24CXX contains an internal address counter which
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. C 09/01/2001
5
IS24C01-2 IS24C01-3 IS24C02-2 IS24C02-2 IS24C04-2 IS24C04-3 IS24C08-2 IS24C08-3 IS24C16-2 IS24C16-3
Vcc
ISSI
IS24Cxx
(R)
SDA SCL
Master Transmitter/ Receiver
Typical System Bus Configuration
SCL from Master
1
8
9
Data Output from Transmitter
tAA tAA
Data Output from Receiver
ACK
Output Acknowledge
STOP Condition
SDA
START and STOP Conditions
START Condition
SCL
6
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. C 09/01/2001
IS24C01-2 IS24C01-3 IS24C02-2 IS24C02-3 IS24C04-2 IS24C08-2 IS24C08-3 IS24C16-2
Data Validity Protocol
IS24C04-3 IS24C16-3
ISSI
Data Stable
(R)
Data Change
SCL
Data Stable
SDA
Slave Address
BIT 7 6 5 4 3 2 1 0
1
BIT 7
0
6
1
5
0
4
A2
3
A1
2
A0
1
R/W
0
IS24C01 IS24C02
1
BIT 7
0
6
1
5
0
4
A2
A1
B0
R/W
0
IS24C04
3
2
1
1
BIT 7
0
6
1
5
0
4
A2
B1
B0
R/W
IS24C08
3
2
1
0
1
MSB
0
1
0
B2
B1
B0
R/W LSB
IS24C16
Byte Write
S T A R T W R I T E A C K M S B L M S S B B R/W S T O P A C K
Device Address
Word Address A C K
Data
SDA Bus Activity
Page Write
S T A R T W R I T E A C K M S B L S B R/W
Device Address
Word Address (n) A C K
Data (n) A C K
Data (n+1) A C K
Data (n+P*) A C K
S T O P
SDA Bus Activity
* P = 7 for IS24C01 and IS24C02 P = 15 for IS24C08 and IS24C16
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. C 09/01/2001
7
IS24C01-2 IS24C01-3 IS24C02-2 IS24C02-2 IS24C04-2 IS24C04-3 IS24C08-2 IS24C08-3 IS24C16-2 IS24C16-3
Current Access Read
S T A R T SDA Bus Activity M S B L S B R/W
ISSI
S T O P
(R)
Device Address
R E A D A C K
Data
N O A C K
Random Access Read
S T A R T SDA Bus Activity M S B W R I T E A C K L S B R/W DUMMY WRITE
Device Address
Word Address (n) A C K
S T A R T
Device Address
R E A D A C K
Data n
S T O P
N O A C K
Sequential Read
R E A D A C K
Device Address SDA Bus Activity
Data Byte n A C K
Data Byte n+1 A C K
Data Byte n+2 A C K
Data Byte n+X
S T O P
N O R/W A C K
8
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. C 09/01/2001
IS24C01-2 IS24C01-3 IS24C02-2 IS24C02-3 IS24C04-2 IS24C08-2 IS24C08-3 IS24C16-2
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VS VP TBIAS TSTG IOUT Parameter Supply Voltage Voltage on Any Pin Temperature Under Bias Storage Temperature Output Current
IS24C04-3 IS24C16-3
Value 0.5 to +6.25 -0.5 to Vcc + 0.5 -40 to +85 -65 to +150 5 Unit V V C C mA
ISSI
(R)
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING RANGE
(IS24C01-2, IS24C02-2, IS24C04-2 IS24C08-2, & IS24C16-2) Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 1.8V to 5.5V 1.8V to 5.5V
OPERATING RANGE
(IS24C01-3, IS24C02-3, IS24C04-3, IS24C08-3, & IS24C16-3) Range Commercial Ambient Temperature 0C to +70C VCC 2.5V to 5.5V
CAPACITANCE(1,2)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF
Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, Vcc = 5.0V.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. C 09/01/2001
9
IS24C01-2 IS24C01-3 IS24C02-2 IS24C02-2 IS24C04-2 IS24C04-3 IS24C08-2 IS24C08-3 IS24C16-2 IS24C16-3
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter VOL1 VOL2 VIH VIL ILI ILO Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VIN = VCC max. Test Conditions VCC = 1.8V, IOL = 0.15 mA VCC = 2.5V, IOL = 1.0 mA Min. -- -- VCC
X
ISSI
Max. 0.2 0.4 0.7 VCC + 0.5 VCC
X
(R)
Unit V V V V A A
-1.0 -- --
0.3
3 3
Notes: VIL min and VIH max are reference only and are not tested.
POWER SUPPLY CHARACTERISTICS
Symbol Parameter ICC1 ICC2 ISB1 ISB2 Vcc Operating Current Vcc Operating Current Standby Current Standby Current Test Conditions READ at 100 KHz (Vcc = 5V) WRITE at 100 KHz (Vcc = 5V) Vcc = 1.8V Vcc = 5.5V Min. -- -- -- -- Max. 1.0 3.0 4.0 8.0 Unit mA mA A A
AC ELECTRICAL CHARACTERISTICS
Symbol Parameter fSCL T tLOW tHIGH tBUF tSU:STA tSU:STO tHD:STA tHD:STO tSU:DAT tHD:DAT tDH tAA tR tF tWR Test Conditions 1.8V-5.5V Min. Max. 0 -- 4.7 4 4.7 4.7 4.7 4 4 200 0 100 0.1 -- -- -- 100 100 -- -- -- -- -- -- -- -- -- -- 4.5 1000 300 10 2.5V-5.5V Min. Max. Unit 0 -- 1.2 0.6 1.2 0.6 0.6 0.6 0.6 100 0 50 0.1 -- -- -- 400 50 -- -- -- -- -- -- -- -- -- -- 0.9 300 300 5 KHz ns s s s s s s s ns ns ns s ns ns ms
SCL Clock Frequency Noise Suppression Time(1) Clock LOW Period Clock HIGH Period Bus Free Time Before New Transmission(1) Start Condition Setup Time Stop Condition Setup Time Start Condition Hold Time Stop Condition Hold Time Data In Setup Time Data In Hold Time Data Out Hold Time SCL LOW to SDA Data Out Change Clock to Output SCL LOW to SDA Data Out Valid SCL and SDA Rise Time(1) SCL and SDA Fall Time(1) Write Cycle Time
Note: 1. This parameter is characterized but not 100% tested.
10
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. C 09/01/2001
IS24C01-2 IS24C01-3 IS24C02-2 IS24C02-3 IS24C04-2 IS24C08-2 IS24C08-3 IS24C16-2
AC WAVEFORMS
IS24C04-3 IS24C16-3
ISSI
tSU:STO
(R)
tR
tF
tHIGH
tLOW
SCL
tSU:STA tHD:STA tHD:DAT tSU:DAT tBUF
SDAIN
tAA
tDH
SDAOUT
Bus Timing
SCL
SDA
8th BIT WORD n
ACK
tWR
STOP Condition START Condition
Write Cycle Timing
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. C 09/01/2001
11
IS24C01-2 IS24C01-3 IS24C02-2 IS24C02-2 IS24C04-2 IS24C04-3 IS24C08-2 IS24C08-3 IS24C16-2 IS24C16-3
ISSI
(R)
ORDERING INFORMATION Commercial Range: 0C to +70C Voltage
Frequency Range 100 KHz 1.8V to 5.5V Part Number IS24C01-2P IS24C01-2G IS24C01-2S IS24C01-2Z IS24C02-2P IS24C02-2G IS24C02-2S IS24C02-2Z IS24C04-2P IS24C04-2G IS24C08-2P IS24C08-2G IS24C08-2Z IS24C16-2P IS24C16-2G IS24C01-3P IS24C01-3G IS24C01-3S IS24C01-3Z IS24C02-3P IS24C02-3G IS24C02-3S IS24C02-3Z IS24C04-3P IS24C04-3G IS24C08-3P IS24C08-3G IS24C08-3Z IS24C16-3P IS24C16-3G Package 300-mil Plastic DIP Small Outline (JEDEC STD) MSOP TSSOP 300-mil Plastic DIP Small Outline (JEDEC STD) MSOP TSSOP 300-mil Plastic DIP Small Outline (JEDEC STD) 300-mil Plastic DIP Small Outline (JEDEC STD) TSSOP 300-mil Plastic DIP Small Outline (JEDEC STD) 300-mil Plastic DIP Small Outline (JEDEC STD) MSOP TSSOP 300-mil Plastic DIP Small Outline (JEDEC STD) MSOP TSSOP 300-mil Plastic DIP Small Outline (JEDEC STD) 300-mil Plastic DIP Small Outline (JEDEC STD) TSSOP 300-mil Plastic DIP Small Outline (JEDEC STD)
100 KHz
1.8V to 5.5V
100 KHz 100 KHz
1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 2.5V to 5.5V
100 KHz
400 KHz
400 KHz
2.5V to 5.5V
100 KHz 400 KHz
1.8V to 5.5V 2.5V to 5.5V 2.5V to 5.5V
400 KHz
12
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. C 09/01/2001
IS24C01-2 IS24C01-3 IS24C02-2 IS24C02-3 IS24C04-2 IS24C08-2 IS24C08-3 IS24C16-2
IS24C04-3 IS24C16-3
ISSI
(R)
ORDERING INFORMATION Industrial Range: -40C to +85C
Voltage Frequency Range 100 KHz 1.8V to 5.5V Part Number IS24C01-2PI IS24C01-2GI IS24C01-2SI IS24C01-2ZI IS24C02-2PI IS24C02-2GI IS24C02-2SI IS24C02-2ZI IS24C04-2PI IS24C04-2GI IS24C08-2PI IS24C08-2GI IS24C08-2ZI IS24C16-2PI IS24C16-2GI IS24C01-3PI IS24C01-3GI IS24C01-3SI IS24C01-3ZI IS24C02-3PI IS24C02-3GI IS24C02-3SI IS24C02-3ZI IS24C04-3PI IS24C04-3GI IS24C08-3PI IS24C08-3GI IS24C08-3ZI IS24C16-3PI IS24C16-3GI Package 300-mil Plastic DIP Small Outline (JEDEC STD) MSOP TSSOP 300-mil Plastic DIP Small Outline (JEDEC STD) MSOP TSSOP 300-mil Plastic DIP Small Outline (JEDEC STD) 300-mil Plastic DIP Small Outline (JEDEC STD) TSSOP 300-mil Plastic DIP Small Outline (JEDEC STD) 300-mil Plastic DIP Small Outline (JEDEC STD) MSOP TSSOP 300-mil Plastic DIP Small Outline (JEDEC STD) MSOP TSSOP 300-mil Plastic DIP Small Outline (JEDEC STD) 300-mil Plastic DIP Small Outline (JEDEC STD) TSSOP 300-mil Plastic DIP Small Outline (JEDEC STD)
100 KHz
1.8V to 5.5V
100 KHz 100 KHz
1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 2.5V to 5.5V
100 KHz
400 KHz
400 KHz
2.5V to 5.5V
400 KHz 400 KHz
2.5V to 5.5V 2.5V to 5.5V 2.5V to 5.5V
400 KHz
ISSI
(R)
Integrated Silicon Solution, Inc.
2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www.issi.com
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. C 09/01/2001
13

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